Apparatus for producing smooth and continuous graphic displays from intermittently sampled data

ABSTRACT

A display apparatus includes a computational circuit that is connected to the output of a memory to introduce between a stored digital representation of successive sampled data points, by an interpolation method, additional virtual or interpolated data points. The interpolated data points are computed in accordance with the magnitudes of the separations or differences in value between the sampled data points. In a CRT display or hard copy recorder, this allows a higher cathode ray sweep speed, and hence, a higher density of raster lines, and consequently, an improvement in resolution, smoothness and continuity of the display, for a given size memory.

BACKGROUND OF THE INVENTION

1. FIELD OF THE INVENTION

This invention relates generally to the production of graphic displaysof data signals, for example, analog physiological signals such as anelectrocardiogram, and relates particularly to sampling type raster scandevices such as display cathode ray tubes or hard copy recorders whereinit is necessary to have a closely spaced raster for good resolution andsmooth interconnection of the data points in order that the traces orcurves being displayed may give the appearance of continuous lines.

2. DESCRIPTION OF THE PRIOR ART

Graphic display apparatus for providing single or multichannel analogdisplays and/or records of the amplitude variations of sampled analogdata signals are known in the prior art. In one such known form ofapparatus, the curves or traces, as plotted on the screen of a cathoderay tube (CRT), comprise a multitude of separated elements or dotsinstead of continuous lines or traces. Specifically, the plotting ofsuch traces is effected by momentarily unblanking a normally blankedcathode ray beam at points along the successive scan or sweep pathswhich form the raster, depending upon the amplitudes of the sampledinput analog data signals under measurement. Traces of this kindcomprising many dots on the screen of the CRT obviously presentdifficulties in interpretation and analysis.

In another such known form of apparatus, graphic displays are producedfrom intermittently sampled analog data signals by a so-called connectedsampling method that yields substantially continuous, and hence, morediscernible curves, notwithstanding the intermittent nature of thesampled data from which the curves are produced. In this form ofapparatus, the traces are obtained by producing successive substantiallyparallel lines on a display medium, for example, a photosensitive recordsheet that is arranged to move past the face of a CRT that is operatedin a line scan mode. Each of such lines extend between two points oneach of the successive sweeps of the cathode ray beam. Between these twopoints the beam is unblanked. The positions of the points represent,respectively, a corresponding two, consecutively derived ones of thesampled data values. A requirement of this prior art apparatus is that asampling and comparison step be performed for each sweep and displayedline constituting the trace. An example of a method and apparatus forproducing such a connected sampling graphic display from intermittentlysampled analog data is shown in U.S. Pat No. 3,605,109 that was issuedon Sept. 14, 1971 to Peter R. Lowe and Tommy N. Tyler.

Display apparatus in which the variations in a sampled measured analogdata value are converted to digital measured quantities which are storedin a suitable memory before being displayed is also known in the art.Such apparatus provides a display of the variations over a period oftime of the analog data value. In such apparatus the sampled measuredanalog values are stored as individual digital values or data points inan image repeating or recirculating memory. An example of such anapparatus is shown in U.S. Pat. No. 3,653,027 that was issued on Mar.28, 1972 to David W. Scheer. As there disclosed, an analog-to-digitalconverter is provided to produce the sampled derived to digital measuredquantities. The digital information is recirculated in the memory at amuch higher rate than that at which the measured digital values areentered into the memory. Blocks of information are read out of thememory at the memory recirculating frequency. The blocks of information,as read out, are converted back to analog form by a digital to analogconverter, and are then presented to the circuit of a cathode ray tubethrough a comparing means. The cathode ray tube circuit includes a highspeed vertical sweep signal and a low speed horizontal sweep signalmeans. A beam intensity or so-called Z-axis modulation means isactivated when the comparing means senses a substantial equality betweenthe analog signal to be displayed and a reference signal related to thehigh speed sweep signal. Specifically, a normally blanked cathode raytube beam is unblanked momentarily, when a digital measured value isdelivered from the memory, at a position along a vertical sweep orraster line dependent upon the value of the measured value. Therepresentation of the variations in the analog data value appears uponthe screen or face of the cathode ray tube as illuminated dots or lightpoints.

A disadvantage of such prior art apparatus is that the dots or lightpoints do not provide smooth and continuous traces or curves. Smoothingout of the traces or curves to make them appear more continuous could beaccomplished by providing a raster with more closely spaced lines. Whilethis is a possible solution, it is subject to a serious disadvantage.This is because of the requirement, with the prior art apparatus, evenif the aforementioned connected sampling technique were employed, thateach raster line must correspond to a data point in the digital memory.That is to say, with the prior art apparatus, the memory must store adata point or value for each raster line. Thus, the larger the number ofraster lines that are provided, the larger the memory must be. Thus, thecost of the memory is increased in proportion to the number of rasterlines. Since memory is expensive, the provision of more closely spacedraster lines to the known prior art apparatus to achieve smoother andcontinuous traces or curves has added significantly to the cost of theapparatus.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide animproved method of and apparatus for producing a graphic display fromintermittently sampled data, which apparatus yields smooth andcontinuous traces or curves that comprise faithful reproduction of thedata notwithstanding the intermittent nature of the sampled data used asthe information from which the curves are produced.

Another object of the invention is to provide an improved apparatus forproviding a cathode ray tube display or hard copy record of highresolution from sampled data, comprising a faithful representation ofthe data, in which apparatus a one-to-one correspondence between rasterlines and sampled data points in the memory is not required for highresolution, whereby for a given desired resolution fewer stored datapoints in the memory are required and a smaller and less expensivememory may be employed.

In accomplishing these and other objects, the apparatus of the presentinvention departs from the techniques employed in the prior art byintroducing between sampled data points on the display or hard copyrecord, by an interpolation method, additional virtual data points whichare computed in accordance with the magnitudes of the separations ordifferences in value between the sampled data points. By employing thisinterpolation method, it is possible to provide a higher density ofraster lines and illuminated points for a memory of given capacity. Thenet result is an improvement in resolution, smoothness and continuity ofdisplay for a given memory capacity.

For convenience such virtual data points are also referred to herein asinterpolated data points. When, for example, three interpolated datapoints are introduced between successively sampled data points, thedensity of the raster lines may be increased by a factor of four for thesame number of sampled data points stored in the memory.

This data interpolation method is used where there is a fixed distance(ΔT) between adjacent data points in the memory. The technique can beextended however, to variable distances between data points. Asdisclosed herein the interpolation method divides the vertical or Ydistance between data points into four segments. As those skilled in theart will understand, however, the Y distance between data points may bedivided into 2^(n) segments where n = 1, 2, 4, . . . to obtain thedesired resolution.

The basic technique for effecting the interpolation can be accomplishedeither by a pre-programmed general purpose digital computer or by hardwired logic. An algorithm is provided for calculating the values of theinterpolated segments. This algorithm basically comprises thecalculation ΔY = Y₂ - Y₁, obtaining Δ Y/4, and then adding ΔY/4 to Y1four times, where Y1 is a first stored data point and Y2 is the nextsuccessive stored data point. This presentation is synchronized with theraster line generation in such a manner that the vertical positions ofthe illuminated interpolated line segments on the face of the cathoderay tube are in accordance with the relative amplitudes of the data endpoints, Y.sub. 1 and Y₂. The values of the data signals, including theinterpolated signals, are presented to a comparator circuit arrangementfor unblanking the beam of a CRT once during each vertical sweep orraster line for a time period related to the distance between the Ysegment end points.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention may be had from thefollowing detailed description when read in connection with theaccompanying drawings wherein:

FIG. 1 is a diagram of a single channel display-producing apparatusaccording to the present invention operating according to the novelmethod thereof:

FIG. 2 is a representation which illustrates the nature of the curvesproduced according to the method and apparatus of the present invention;

FIG. 3 shows a hard wired logic circuit for effecting the interpolationcomputations in the apparatus of FIG. 1;

FIG. 4 is a diagram showing the clock timing for the beam comparator ofFIG. 3;

FIG. 5 is a flow chart illustrating the algorithm for the computationalcircuitry of the FIG. 1 apparatus; and

FIG. 6 illustrates the circuit for the digital beam comparator for theY-trace data in the apparatus of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT THE APPARATUS OF FIG. 1

FIG. 1 shows the path 1 of a cathode ray or electron beam of a CRT 2that is operated on a line scan mode, a Z-axis modulation or beamintensity controlling cathode 3, horizontal deflection plates 4, adisplay screen 5 and a source of high voltage shown at 6. The CRt 2 alsoincludes a fiber optics array or strip (not shown) that is inserted intothe faceplate 7. A photosensitive record sheet 8 is advanced by asuitable servo shown at 9, at a predetermined rate upward, as seen inFIG. 1, past the fiber optics strip from a supply of the photosensitiverecord sheet.

An analog signal to be displayed, for example, an electrocardiogramsignal derived from a sensing device shown at 10, is applied to an inputterminal of an analog to digital (A-D) converter 11. A - D converteroutput is connected to suitable update control logic circuitry shown at12 to the input of an image repeating or recirculating memory 13. Theoutput of the recirculating memory 13, comprising 10 lines although notshown in FIG. 1, is connected to the input of interpolationcomputational circuitry shown at 14. The output of the computationalcircuitry 14 is connected to the input of a digital beam comparatorcircuit shown at 15. The output of the digital beam comparator circuitis applied to a blanking circuit shown at 16 for the cathode ray beam ofthe CRT 2.

Horizontal synchronizing pulses for causing repetitive sweeping of thecathode ray beam along the aforementioned fiber optics strip aresupplied to the horizontal deflection plates 4 under the control of theupdate control logic circuitry 12. To that end, an output of circuit 12is connected to the input of an amplifier control shown at 17. Theoutput of amplifier control 17 is connected to the input of a horizontaldeflection amplifier shown at 18. The output of the latter is connectedto the horizontal deflection plates 4 of the CRT 2. The cathode ray orelectron beam is repetitively swept by the horizontal deflection plates4 along the fiber optics strip of the CRT 2. Normally, the cathode raybeam is blanked and unless unblanked the signals applied to thehorizontal deflection plates ane not effective to produce marks ortraces on the photosensitive sheet 8. The cathode ray beam is arrangedto be selectively unblanked under the control of the blanking circuit 16which, in turn, is controlled by the beam comparator circuit 15. Alatensifier shown at 19 is provided to latensify the latent imagesproduced on the photosensitive sheet 8, in a manner known in the art.The intensity of the radiation produced by the latensifier is controlledby the logic circuit 12 in accordance with the speed at which thephotosensitive sheet 8 is moved past the face plate of CRT 2. As shownin FIG. 1, a manual control device, for example, a push button selectorswitch 20, is provided for the logic circuit to facilitate adjustment inthe said speed of the photosensitive sheet 8.

While only a single channel is shown in FIG. 1, it will be understoodthat the CRT 2, which may be a large screen CRT, may be employed toservice a number of different channels of data sequentially. Informationfor this channel of data as well as for other channels, when provided,is stored in the recirculating memory 13 and is selectively played outresponsively to signals applied thereto by the update control logiccircuitry 12.

The block diagram of FIG. 1 shows the essential features required forone channel. The incoming data on the input of A - D converter 11 isdigitized, for example, to 10 bit resolution, at a constant high ratewhich may be 7 Khz. This data goes into the update control logiccircuitry 12 which outputs one word of data at a rate determined by thepaper speed, and which may be as high as 700 Hz. or as low as severalHz., for example 3.5 Hz.

Words representing adjacent sampled data values in the memory 13 areapplied to the input of the interpolation computational circuitry 14 ata rate demanded by the speed at which the photosensitive sheet 8 ismoved past the faceplate of the CRT 2. The computational circuitry 14 isoperative, in a manner described hereinafter, to calculate, at a ratedetermined by the paper speed, several successively increasing ordecreasing values intermediate the last two values presented to itsinput by the recirculating memory 13. The last mentioned valuesincluding the calculated intermediate values are applied in sequence tothe input of the beam comparator circuitry 15. The output of the latteris applied to the blanking circuit 16 and presented thereby to the beamcontrolling cathode of the CRT 2. At the same time, as noted, thehorizontal axis is swept, desirably although not necessarily, in alinear fashion. The resulting path of the cathode ray beam of the CRT 2and the display provided thereby is illustrated in FIG. 2 for a typicalanalog input signal applied to the input of A - D converter 11.

THE REPRESENTATION OF FIG. 2

FIG. 2 shows the recording on photosensitive sheet 8 of the analogsignal, applied by the device 10 to an input terminal of A - D converter11, obtained by the recording technique according to the presentinvention. As seen in FIG. 2, the series of light solid lines identifiedas Sweep No. 1, Sweep No. 2, etc. represent successive scan or sweeppaths of the cathode ray beam along the length of the fiber optics stripof CRT 2, assuming time to be increasing toward the right. The dashlines between the sweep paths, indentified as Retrace No. 1, Retrace No.2, etc. represent the retrace, return, or flyback paths of the beam. Forpurposes of illustration, the lines have been shown with greatlyexaggerated spacing along the time axis.

The heavy line indicated by the letter S in FIG. 2 represents the actualvalues of the analog data signal under measurement with respect to time,that is, the varying signal derived from the sensing device 10, as seenin FIG. 1. The line segments shown in heavy lines along Sweep Nos. 1through 4 show the line segments produced on the screen of the CRT 2 asthe electron beam is unblanked during the successive sweeps fo the beam.It is noted that these segments are produced in an indicating or displayperiod that follows a measurement period in which the signalrepresenting the data signal is measured. Thus the lowest value of thedata signal at the time t₁ is shown as equal to the value at point Y₁ ofthe line segment along Sweep No. 1. The value b of the data signal attime t₂ is shown as equal to the maximum value of the line segment alongSweep No. 4. The length of the line segments along each of Sweep Nos. 1through 4 are each equal to one-fourth of the vertical distance betweenpoints Y₂ and Y₁. If the distance Y₂ - Y₁ = Δ Y, then the length of theline segments is equal to ΔY/4, as shown in FIG. 2. This introduction ofa plurality of line segments between the points Y1 and Y2 providessignificantly better display resolution, as those skilled in the artwill readily understand. Additionally, the introduction of theintermediate line segments contributes significantly to the smoothnessand continuous appearance of the trace or curve formed by the successiveline segments on the photosensitive sheet 8.

THE COMPUTATIONAL CIRCUITRY OF FIG. 3

The circuit 14 of the FIG. 1 apparatus for effecting the interpolationcomputations is illustrated in hard wired form in FIG. 3. As seen inFIG. 3, ten lines from the output of the recirculating memory 13 areconnected to the inputs of two sets of latches which are indicatedgenerally at 21 and 23. Each set of latches includes ten latches each ofwhich may be of D flip-flop form. The ten lines from the outputs of thelatches indicated at 21 are connected to input terminals designated A₀ -A₁₀ of an 11 bit adder indicated at 22. The ten lines from the output ofthe latches indicated at 23 similarly are connected to the inputterminals B₀ - B₁₀ of the adder 22. The ten lines from the latches 23 tothe adder 22, however, each include an inverter. The inverters have beengenerally designated by the numeral 24.

The latches 21 are arranged to transmit to the adder 22 a digitalrepresentation of a first data point, for example, that designated Y₂ inFIG. 2, stored in the memory 13. Similarly, the latches indicated at 23and the associated inverters 24 are arranged to transmit to the adder 22a digital representation of an adjacent data point, for example thatdesignated Y₁ in FIG. 2, stored in the memory 13. To this end,activating signals are sequentially applied to the sets of latches 23and 21 in synchronism with the successive outputting by therecirculating memory 13 of the digital representations of adjacent datapoints. The activating signals are applied to the latches 23 and 21 andto the recirculating memory 13 from the update control logic circuitry12.

The function of the apparatus of FIG. 3 is to respond to the digitalrepresentations outputted by the memory 13 of adjacent pairs of datapoints to produce a plurality of intermediate digital representations ofdata points intermediate each of said pairs of data points. Suchintermediate digital representations comprise the aforementionedinterpolated or virtual values. For convenience, the pairs of adjacentdata points will hereinafter be referred to as Y_(n) and Yn+1 and are soindicated in FIG. 3.

The digital representation Y_(n) is first stored in the latches 23 andthen the digital representation Yn+1 is stored in the latches 21. Bothof these storage operations and the outputting of information by thememory 13, are accomplished during a retrace period of the cathode raybeam 1 of CRT 2 when it has been determined, as hereinafter described,that new data points, and therefore, new interpolated line segments aredesired. It will be seen by reference to FIGS. 2 and 4 that each of thesuccessive line segments are produced during an individual sweep of thecathode ray beam. FIG. 4 shows the clock timing diagram for the beamcomparator circuitry 15. Each such sweep is effected between counts 0and 1023 of a divide by 1140 counter, not shown, but embodied in theupdate control logic circuitry 12. The said counter provides suitableactivating signals to the latches 21 and 23 whereby the storage of thedigital representations of Y_(n) and Yn+1 and successive, new digitalrepresentations are stored in the respective latches 23 and 21 afterevery fourth sweep, during the retrace period, that is, between counts1024 and 1139 of the counter. Count 1140 of the counter is a reset countfor the counter. The digital representations of the data value pairs,Y_(n) and Yn+1 remain stored in the latches during the display periodfor those data value pairs, that is, through four successive sweeps ofthe cathode ray beam. During the retrace period comprising counts 1024through 1139 of the counter following each such display period, newvalues of adjacent data points, Y_(n) and Yn+1 of the data stored in therecirculating memory are stored in the latches 23 and 21. These values,as noted, remain stored in the latches through four successive sweepperiods, each comprising counts 0 through 1023 of the counter, and thetimes of the intermediate retrace periods, needed to display four linesegments. This action is continually repeated.

In the operation of the FIG. 3 apparatus, the 11 bit adder 22 operatesto subtract Y_(n) from Yn+1 to determine the difference, designated ΔY,between the said two values. The 11 bit adder 22 may be of known typeand provides the result of Yn+1 minus Y_(n) in 2's complement. Adder 22has the carry input set at a logical 1 to provide 2's complementsubtraction. The 2's complement, as is known, provides a representationof the difference between Yn+1 and Y_(n) in positive and negativevalues. Thus, ΔY may be represented as a positive number or it may be anegative number. The 2's complement defines whether the number ispositive or negative and also provides the value of the number.

As seen in FIG. 3, the summation output terminals Σ 0 through Σ11 of the11 bit adder 22 are applied to the B₀ through B₁₂ input terminals of a12 bit adder indicated at 25. The B₁₁ and B₁₂ terminals of the adder 25are connected together. The summation output terminals Σ0 through Σ12 ofthe adder 25 are connected to the input terminals B₀ through B₁₂ of a 2to 1 data selector indicated at 26. The output from latches 23 isdirectly connected, that is, independently of the inverters 24, to theA₂ - A₁₂ inputs of the data selector 26. Thus, the digitalrepresentation of data point Y_(n) is applied directly to the lastmentioned inputs of the data selector 26. The output terminals 0₀through 0₁₂ of the data selector 26 are connected to the input terminalsof an accumulator indicated at 27. The latter comprises 12 flip flops.The output terminals Q₀ through Q₁₂ of the accumulator 27 are connectedin a feedback manner to the input terminals A₀ through A₁₂ of the 12 bitadder 25. Additionally, as seen in FIG. 3, the output terminals 0₂ to0₁₂ of the data selector 26 are connected to the input of the beamcomparator circuitry 15.

Activating control signals are applied to the data selector 26 and theaccumulator 27 from the update control logic circuitry 12. These signalsare applied during the retrace periods of the cathode ray beam 1 of CRT2, specifically between counts 1024 and 1139 of the divide by 1140counter. Upon the assumption that the data selector is gating the outputof adder 25 to the input of accumulator 27, then the adder 25 is addingΔ Y/4 to what is in the accumulator. Clocking the accumulator 27 loadsin what was previously in the accumulator plus Δ Y/4. The carry inputinto adder 25 is held at logical `0`, grounded, to provide normaladdition.

By way of illustration and not by way of limitation, it is noted thatthe several components or devices shown in symbolic form in FIG. 3, may,if desired, be commercially available types offered by Texas Instrumentsas listed below:

    ______________________________________                                        Latch 21        Two Type SN74174 units                                        Latch 23        Two Type SN74174 units                                        Adders 22, 25   Three Type SN74283 units                                      Data Selector 26                                                                              Three Type SN74157 units                                      Accumulator     Two Type SN74174 units                                        ______________________________________                                    

THE Y-TRACE INTERPOLATOR ALGORITHM OF FIG. 5

Referring now to FIG. 5, there is shown a flow chart which illustratessymbolically the manner in which the computational circuitry 14generates successive words representative of the intermittent andsuccessive line segments Δ Y/4 along the successive traces designatedSweep Nos. 1 through 4, as is seen in FIG. 2. For convenience ofillustration, the segments along the successive sweeps have beendesignated segment 1, segment 2, segment 3 and segment 4. As noted, allof the segments between the adjacent data points Y_(n) and Yn+1 orbetween the data points Y₁ and Y₂, Y₂ and Y₃, as shown in FIG. 2 are ofequal length. Thus, the segments during successive display periods maybe similarly designated, and in any particular display period, thesegments also are all of the same length. The actual length of thesegments in different display periods will depend upon the verticaldistance between the successive data points, for example, Y₃ - Y₂, Y₄ -Y₃, etc., as seen in FIG. 2.

Specifically, by reference to FIG. 5, it will be seen that the algorithmfirst inquires as to whether the counter of the update control logiccircuitry 12 is in retrace, that is counts 1024 through 1139 of thedivide by 1140 counter. If not, the apparatus illustrated in FIG. 3waits until the said counter is in retrace. If the said apparatus is inretrace, the value of new line segments may require calculation. Thenext inquiry is to determine which segment (1, 2, 3 or 4) the beam willbe on next. Having made a determination that the next such end segmentis the first, the algorithm then provides for fetching from therecirculating digital memory 13 the data values for the points Y_(n) andYn+1. This results in the generation of a signal from the update logiccircuitry 12 to provide the sequential outputting of the data signalsY_(n) and Yn+1 from the memory 13 and their storage in the latches 23and 21, respectively. From there they go into the 2's complement adder22. The algorithm then provides for the determination of Yn+1 and Y_(n)to provide Δ Y in 2's complement. This representation comes out of theadder 22. Following this determination and activation the algorithmspecifies shifting Δ Y to the right two places to determine Δ Y/4. Thisoperation is performed by the hard wired inputs to the 12 bit adder 25.As is known, in binary notation, the shifting of a number to the rightresults in actual division of the number by two each time such a shiftis made.

By reference to FIG. 3, it will be seen that the extreme right bit ofY_(n) comes into terminal B₀ of adder 22 and comes out of Σ 0. This bitcontinues on down to the output terminal on the extreme right of thedata selector 26, as seen in FIG. 3. The digital word, however, that isfed to the beam comparator 15 is taken from the output terminal 0₂ tothe output terminal 0₁₂ of the data selector 26. The two right hand bits0₀ and 0₁ are omitted. Taking Y_(n) applied to input terminals A₂through A₁₂ of data selector 26, and having the Δ Y over at the rightten bits is equivalent to a shift to the right of two bits. Δ Y thus isshifted to the right by two places by the hard wiring into the 12 bitadder 25. The first value needed in the accumulator 27 is Y_(n). Thisvalue can be added to the value Δ Y/4. The way Y_(n) is stored in theaccumulator 27 is by means of the 2 to 1 data selector 26. Thus, as seenin FIG. 3 and as was previously mentioned, the value Y_(n), directly outof the latches 23, is connected into the input terminals A₂ through A₁₂of the data selector 26. The connection of this digital representationis into the 10 left bits. The two right bits A₀ and A₁, are 0. Thiscorresponds with the digital word that is to be applied to the beamcomparator 15.

Having effected the storage of Y_(n) in the accumulator, the nextinquiry of the algorithm, as seen in FIG. 5, is the apparatus about toproduce the first trace segment of a display period, that is, segment 1.If so, the digital word representing Y_(n) is given to the beamcomparator 15. Then the algorithm provides for the addition of Δ Y/4 toY_(n). The next inquiry is whether the apparatus is about to producesegment 1 or segment 2. If in the affirmative, the digital word forY_(n) + Δ Y/4 is given to the beam comparator. Next, the value Δ Y/4 isadded to the quantity Y_(n) + Δ Y/4 to provide the digitalrepresentation for Y_(n) + 2 Δ Y/4. Again, an inquiry is then made as tothe trace segment that is about to be produced, namely, segment 2 orsegment 3. If so, the digital word representing Y_(n) + 2 Δ Y/ 4 isgiven to the beam comparator. Then the value Δ Y/4 is added to thequantity Y_(n) + 2 Δ Y/4 to provide the value Y_(n) + 3 66 Y/4. Afurther inquiry as to the segment about to be produced is then made,that is, segment 3 or segment 4. If affirmative, the digital word forthe quantity Y_(n) 3ΔY/4 is given to the beam comparator. Then the valueΔ Y/4 is added to the quantity Y_(n) + 3ΔY/4 to provide the valueY_(n) + 4ΔY/4. An inquiry is then made as to whether the apparatus isabout to produce segment 4. If the latter the digital word for thequantity Y_(n) + 4ΔY/4 is given to the beam comparator. Then, thealgorithm provides for the stopping of further such inquiries anddirects the apparatus to go back and wait for the next retrace period ofthe divide by 1140 counter.

THE BEAM COMPARATOR CIRCUIT OF FIG. 6

FIG. 6 shows the beam comparator circuit of the FIG. 1 apparatus. Asshown, the circuit of FIG. 6 includes a first group of flip-flops 30, asecond group of flip-flops 31, a first digital comparator 32, a seconddigital comparator 33, an AND gate 34, flip-flops 35, 36 and 37, anEXCLUSIVE OR gate shown at 38, a one-shot shown at 39, and an OR gate40. The output of the OR gate 40 is connected to the blanking controlcircuit 16, as seen in FIG. 1.

Specifically, the circuit arrangement of FIG. 6 is operative to turn onthe cathode ray beam of the CRT 2 when the vertical sweep or raster lineas seen in FIG. 2 crosses the first Y value, and is operative to turnoff the beam when the sweep line crosses the second Y value. If the twoY values are equal, the one-shot 29 momentarily turns on the beam whenthe common Y value is crossed.

The update control logic circuitry 12, as mentioned hereinbefore,includes a divide by 1140 counter, which provides, in addition to thesignals previously mentioned, a signal that is in synchronism with thesweep signal applied to the deflection plates 4 of the CRT 2. Thissignal count is applied to the clock inputs of each of the digitalcomparators 32 and 33. Retrace signals also are applied from the controllogic circuitry 12 to the reset terminals of the flip-flops 35, 36, and37 to reset them. With this arrangement, the sweep of the cathode raybeam effectively is controlled by the counter. The sweeps respectivelyoccur during counts 0 to 1024 of the counter and the beam repetitivelyis held in retrace for counts 1025 through 1139.

Thus, there has been provided, in accordance with the present invention,an apparatus for producing a faithful display of the variations inamplitude with time of an input data signal. To that end, the datasignal is repetitively sampled to derive a succession of values each ofwhich represents a successive amplitude condition of the signal, andsuccessively and linearly interpolated amplitude conditions of thesignal are derived and introduced between the said first mentionedsuccessive amplitude conditions of the signal. The successive amplitudeconditions of the signal including the interpolated conditions are usedto produce substantially parallel line segments in each of individuallyassociated sweeps of the cathode ray beam of the CRT. Each of such linesegments so produced is substantially continuous whereby a smooth andcontinuous trace of the variations in amplitude of the input data signalderived from sensing device 10 is produced.

Also, there has been provided, in accordance with the present invention,an apparatus for producing a higher degree of resolution for the samesize memory storage capacity than has been available with prior artapparatus. With the arrangement illustrated and described, the storagecapacity of the recirculating memory may be smaller in size than thatwhich would be required if the interpolating method and apparatus of thepresent invention were not employed. While the algorithm provided forcalculating the values of the interpolated segments contemplates adivision of Δ Y by four, and then adding Δ Y/4 to Y1 four times, whereY1 is the first stored data point and Y2 is the next successive storeddata point, it will be apparent to those skilled in the art that adifferent algorithm may be employed, as mentioned hereinbefore. Forexample, if an algorithm contemplating Δ Y to be divided by 8 wereprovided, such an algorithm would allow the storage capacity of thememory 13 to be one-eighth that of the prior art for the same degree orresoltuion, and would contribute even further to the smoothness of thetrace or curve produced, within the restraints of the resolution of theCRT beam.

As those skilled in the art will readily understand, the interpolatingtechnique of the present invention may be embodied in a CRT visualdisplay arrangement as well as in the hard copy recording arrangementillustrated in FIG. 1. In the CRT visual display format thephotosensitive sheet 8 and the servomotor drive mechanism would not beemployed. Also, the CRT employed would not require the fiber opticsstrip of CRT 2. Vertical deflection plates as well as horizontaldeflection plates would be required, however, for the CRT. Verticaldeflection signals synchronized with the horizontal sweep signals wouldbe required for the vertical deflection plates, as disclosed, forexample, in said aforementioned U.S. Pat. No. 3,653,027. Such verticaldeflection signals could be supplied by the update control logiccircuitry 12. In a manner similar to that described in said U.S. Pat.No. 3,653,027, the data stored in the recirculating memory 13 would becontinuously updated by new data. As a result the traces observed on theface of the CRT and representing the variations in the input data over aperiod of time would be seen to move across the face of the CRT.Alternatively, in a manner known in the art, new and old data may bemade to remain stationary on the face of the CRT and a vertical bar madeto move from left to right, for example, to erase old data and toreplace it with new data. Desirably, the rate at which new data is madeto replace old data (the update speed) may be controlled by an operator.To that end the update control logic circuitry would be provided with asuitable manually adjustable control component.

The embodiments of the invention in which an exclusive property orprivilege is claimed are defined as follows:
 1. Apparatus for producinga display of the condition of a signal comprising,a display means havinga display medium, first means connected to the source of the signal forproducing a succession of digital value representations,each of whichrepresents a successive condition of the signal, and second meansconnected to said first means to derive from consecutively derived onesof said digital values other digital values intermediate of saidconsecutively derived ones, said second means including a recirculatingmemory in which said succession of digital value representations arestored and which is arranged to output digital value representations ofadjacent stored values of the condition of the signal, a computationalcircuit that is connected to the output of said memory and is responsiveto the digital value representations produced at said output to producedigital representations of values of the condition of the signalintermediate said adjacent stored values, said computational circuitincluding first and second latch means connected to the output of saidrecirculating memory, the digital representations of the first occurringof said adjacent values being stored in the first one of said latchmeans, and the digital representation of the second occurring of saidadjacent values being stored in a second one of said latch means, firstand second adders, each of said adders having first and second sets ofinput terminals and a set of summation output terminals, the output ofsaid second latch means being applied to said first set of inputterminals of said first adder, inverting means, the output of said firstlatch means being connected through said inverting means to said secondset of input terminals of said first adder, the summation outputterminals of said first adder being connected to said first set of inputterminals of said second adder, a data selector having first and secondsets of input terminals and a set of output terminals, connections fromthe output of said first latch means to said first set of inputterminals of said data selector, a connection from the summation outputterminals of said second adder to said second set of input terminals ofsaid data selector, an accumulator having input terminals and outputterminals, a connection from the output terminals of said data selectorto the input terminals of said accumulator, and a connection from theoutput of said accumulator to said second set of input terminals of saidsecond adder and third means includes a digital comparator connected tothe output of said data selector of said computational circuit, saiddigital comparator being operative to respond to the digitalrepresentations produced by said computational circuit to provide asuccession of control signals, and display means controlled by saidcontrol signals to produce substantially parallel lines on said displaymedium,each of said lines being individually representative of a relatedone of said consecutively derived ones and said other values, all ofsaid lines being substantially continuous and extending in theiraggregate length between two points, the positions of which represent,respectively, a corresponding two, consecutively derived ones, of saidvalues.
 2. Apparatus as specified in claim 1 wherein said display meansincludes a cathode ray tube having a screen and means to produce acathode ray beam, wherein said third means includes means to sweep saidcathode ray beam across said screen, and wherein said third meansincludes further means selectively to blank and unblank the said cathoderay beam.